1. Field of the Invention
The present invention relates to clock/data recovery systems and more particularly to a method and apparatus for applying digital techniques to recover clock and data from a serially transmitted data stream.
2. Description of the Related Art
Data transmission systems sometimes incorporate accurate and stable delay elements to generate predetermined width pulses for clock synchronization, clock multiplication, and clock/data recovery. In systems that serially transmit and receive data, clock information is generally embedded within the data stream to provide correct timing for data recovery because there are no separate lines or channels to independently carry the clock signal to the receiver. Clock frequency recovery and phase alignment with the data are typically performed before the received data can be recovered and deserialized.
Traditionally, a Phase Locked Loop (PLL) circuit is employed to recover the clock frequency and align the clock with the data phase. A PLL circuit incorporates a Voltage Controlled Oscillator (VCO) whose frequency is adjusted in response to the frequency of the incoming data. FIG. 5 illustrates the typical configuration of a PLL circuit. The PLL circuit includes a VCO 10 that outputs a phase signal V.sub.C to a phase detector 12. The phase detector 12 generates an error voltage (V.sub.E) based on a comparison of the phase signal V.sub.C with a reference signal (V.sub.R). After passing through a filter 14, the error voltage is supplied to the VCO 10. Accordingly, the phase difference must be constantly detected and so that the error voltage V.sub.E may be appropriately adjusted. The disadvantage of the circuit illustrated in FIG. 5 is that it is very sensitive. Any fluctuations from the outside coupled into the error voltage V.sub.E will influence the frequency F. The benefit of the circuit illustrated in FIG. 5 is that it is analog. Hence, regardless of the frequency or phase variations resulting from noise, the signal is never completely lost.
In operation, the PLL circuit detects the phase error of the recovered clock, or the phase difference between the output of the VCO 10 and the incoming data, and generates an error signal. The low pass filter 14 is used to filter and convert the error signal into a control voltage for driving the VCO 10 and consequently reducing the phase difference. Elimination, or leveling (i.e., obtaining a constant value), of the phase difference results in the VCO 10 outputting a retimed clock that has an established and known phase relationship with the data.
In practice, however, the incoming serial data is often contaminated with various types of noise that result in timing or phase jitter. Consequently, the edges (i.e., the transitions) in the data stream do not always arrive at precisely the same time. Rather, the edges arrive at different (either early or late) times, causing the timing noises (i.e., jitter). Additionally, incorrect phase errors are detected and adjustments to the VCO 10 control are still attempted even when the VCO frequency is the same as, or very close to, the data frequency.
PLL circuits are generally designed to reduce the effect of such jitter sources in the high frequency range by employing special low pass filters. However, such filtering introduces other problems. The control voltage to the VCO 10 is very susceptible to internally generated switching noise, and such susceptibility increases as the operating frequency increases. Furthermore, low pass filters employ large valued components such as capacitors and resistors, resulting in increased manufacturing costs when implemented as monolithic integrated circuits.
One approach to reducing the phase error of the recovered clock is to implement the PLL in a digital form. Such approaches typically employ an adjustable bias voltage, or current, to adjust the delay value of a delay unit in a ring oscillator in order to achieve frequency tuning (or to adjust the phase to match that) of the incoming data. Digital PLLs use digital logic for phase detection, filtering, and (at times) the ring oscillator. In a purely digital PLL system, no bias or ring oscillator is used. Such digital systems are disclosed in U.S. Pat. Nos. 5,457,719; 5,349,612; 5,400,370; 5,367,542; 5,451,894; and 5,264,745. However, digital implementations of PPLs must be specifically designed to accommodate particular data or coding formats, jitter tolerance, or operational frequencies.
In purely digital approaches to clock and data recovery, the phase offset information is stored in a digital format as a code. The code is stored and constantly updated in specially designed register circuits in order to reflect the phase difference as a function of time. Although digital clock/data recovery approaches are less sensitive to noise than analog PLLs under very noisy power supply conditions, they are subject to a "lock up" condition. Under a lock up condition, the system enters an undefined state wherein the stored information is either lost or "locked" and, consequently, unretrievable. This is because unlike analog PLL circuits, where there is always a bias voltage value (regardless of changes in the power supply voltage), a digital system is typically unable to perform a self-recovery lock-ups resulting from a power surge unless a full or partial reset operation is performed.
According to one approach to digital data recovery, various digital "pointers" are used to indicate the delay calibration status and the phase difference between the local clock and the remote clock which is used to send the data over the serial link. The pointers are constantly adjusted based on variations in temperature, supply voltage, and data phase and frequency. Compared to traditional synchronous digital circuits, these adjustment operations are further complicated by the fact that they relate to two asynchronous clock sources. When a power supply surge occurs, there is a possibility that one of the "pointers" can get lost, and subsequently, the recovered clock signal gets lost. User software "watch dog" functions have previously been used to ensure the reliability and automatic recovery from unexpected events. However, in an integrated chip or system, software monitored by the user can only do a system-wide or chip-wide reset. Therefore, a non-graceful recovery process results.
Accordingly, a primary disadvantage associated with current methods of recovering asynchronous signals, such as a clock signal, and data from a serially transmitted data stream is the inability to perform a graceful recovery upon detecting a loss of the clock signal.